The present invention relates generally to semiconductor devices and their fabrication and, more particularly, to testing and analysis of semiconductor dies involving the alteration of the timing margin of the die.
The semiconductor industry has recently experienced technological advances that have permitted dramatic increases in integrated circuit density and complexity, and equally dramatic decreases in power consumption and package sizes. Present semiconductor technology now permits single-die microprocessors with many millions of transistors, operating at speeds of hundreds of millions of instructions per second to be packaged in relatively small, air-cooled semiconductor device packages. As clock frequencies increase, problems associated with the proper timing of various semiconductor die operations increase.
A by-product of such high-density and high functionality is an increased demand for products employing these microprocessors and devices for use in numerous applications. As the use of these devices has become more prevalent, the demand for faster operation and better reliability has increased. Such devices often require manufacturing processes that are highly complex and expensive.
As manufacturing processes for semiconductor devices and integrated circuits increase in difficulty, methods for testing and debugging these devices become increasingly important. Not only is it important to ensure that individual dies are functional, it is also important to ensure that batches of dies perform consistently. In addition, the ability to detect a defective manufacturing process early is helpful for reducing the number of defective devices manufactured.
Traditionally, integrated circuits have been tested using methods including directly accessing circuitry or devices within the integrated circuit. Directly accessing the circuitry is difficult for several reasons. For instance, in flip-chip type dies, transistors and other circuitry are located in a very thin epitaxially grown silicon layer in a circuit side of the die. The circuit side of the die is arranged face-down on a package substrate. This orientation provides many operational advantages. However, due to the face-down orientation of the circuit side of the die, the transistors and other circuitry near the circuit side are not readily accessible for testing, modification, or other purposes. Therefore, access to the transistors and circuitry near the circuit side is from the back side of the die.
One particular type of semiconductor device structure that presents unique challenges to back side circuit analysis is silicon-on-insulator (SOI) structure. Forming a SOI structure involves forming an insulator, such as an oxide, over bulk silicon in the back side of a semiconductor device. A thin layer of silicon is formed on top of the insulator, and circuitry is formed over the insulator. The resulting SOI structure exhibits benefits including reduced switch capacitance, which leads to faster operation. Direct access to circuitry for analysis of SOI structure, however, involves milling through the oxide. The milling process can damage circuitry or other structure in the device. Such damage can alter the characteristics of the device and render the analysis inaccurate. In addition, the milling process can be time-consuming, difficult to control, and expensive.
One aspect of integrated circuit die operation that is important for analyzing dies involves the logic state of various circuitry in the die. Malfunctions or design problems are often related to certain circuitry that is not operating at the proper logic state, or is delayed in getting to or changing from a selected logic state. The detection of selected logic states is useful for various reasons, including determining whether a particular die is operating properly, and for isolating defects in a die. In SOI dies, detecting particular logic states can be difficult, however, for reasons including those stated hereinabove and related to the challenges presented to accessing circuitry in the die for such analysis.
The difficulty, cost, and destructive aspects of existing methods for testing integrated circuits present challenges to the growth and improvement of semiconductor technologies involving SOI structure.
The present invention is directed to a method and system for analyzing a semiconductor die having silicon-on-insulator (SOI) structure in a manner that addresses the above-mentioned challenges. The present invention is exemplified in a number of implementations and applications, some of which are summarized below.
According to an example embodiment of the present invention, a semiconductor die having SOI structure and circuitry in a circuit side opposite a back side is analyzed. In a typical application, a portion of substrate is removed from the back side of the semiconductor die, and an electrical input is capacitively coupled through the insulator portion of the SOI structure. The input is selected to force a state change in circuitry in the die. For example, in one implementation, forcing a state change includes capacitively coupling a voltage to the circuitry and causing the circuitry to take on a selected state and/or isolating the circuitry. The resulting state change is used to evaluate a characteristic of the die.
According to another example embodiment of the present invention, a system is adapted for analyzing a semiconductor die having silicon-on-insulator (SOI) structure and circuitry in a circuit side opposite a back side. The system includes a probe adapted to capacitively couple an electrical input through the insulator portion of the SOI structure and selectively effect a state change to circuitry in the die. A detector is adapted to use the selected state change to evaluate a characteristic of the die.
The above summary of the present invention is not intended to describe each illustrated embodiment or every implementation of the present invention. The figures and detailed description that follow more particularly exemplify these embodiments.